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1 features ? high-density, high-performance, electrically-erasable complex programmable logic device ? 128 macrocells ? 5 product terms per macrocell, expandable up to 40 per macrocell ? 84, 100, 160 pins ? 7.5 ns maximum pin-to-pin delay ? registered operation up to 125 mhz ? enhanced routing resources flexible logic macrocell ? d/t/latch configured flip-flops ? global and individual register control signals ? global and individual output enable ? programmable output slew rate ? programmable output open collector option ? maximum logic utilization by burying a register within a com output advanced power management features ? automatic 10 a standby for ? l ? version ? pin-controlled 1 ma standby mode ? programmable pin-keeper inputs and i/os ? reduced-power feature per macrocell available in commercial and industrial temperature ranges available in 84-lead plcc and 100-lead pqfp and tqfp and 160-lead pqfp packages advanced ee technology ? 100% tested ? completely reprogrammable ? 10,000 program/erase cycles ? 20-year data retention ? 2000v esd protection ? 200 ma latch-up immunity jtag boundary-scan testing to ieee std. 1149.1-1990 and 1149.1a-1993 supported fast in-system programmability (isp) via jtag pci-compliant 3.3 or 5.0v i/o pins security fuse feature enhanced features improved connectivity (additional feedback routing, alternate input routing) output enable product terms transparent-latch mode combinatorial output with registered feedback within any macrocell three global clock pins itd (input transition detection) circuits on global clocks, inputs and i/o fast registered input from product term programmable ? pin-keeper ? option v cc power-up reset option pull-up option on jtag pins tms and tdi advanced power management features ? edge-controlled power-down ? l ? ? individual macrocell power option ? disable itd on global clocks, inputs and i/o for ? z ? parts high- performance ee pld atf1508as atf1508asl rev. 0784m ? 08/01
2 atf1508as(l) 0784m ? 08/01 84-lead plcc top view 100-lead tqfp top view 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 i/o/pd1 vccio i/o/tdi i/o i/o i/o i/o gnd i/o i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o i/o i/o gnd i/o i/o gnd i/o/tdo i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o/pd2 i/o gnd i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o/pd1 i/o vccio i/o/tdi i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o/tdo i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o vccio 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gnd i/o i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o/pd2 i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o i/o i/o i/o 100-lead pqfp top view 160-lead pqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o i/o i/o/pd1 i/o vccio i/o/tdi i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o gnd i/o/tdo i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o vccio i/o i/o 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o/pd2 i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 n/c n/c n/c n/c n/c n/c n/c vccio i/o/tdi i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o/tms i/o i/o i/o vccio i/o i/o i/o i/o i/o i/o i/o n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd i/o/tdo i/o i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o i/o/tck i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o n/c n/c n/c n/c n/c n/c n/c 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 i/o gnd i/o n/c n/c n/c n/c i/o i/o i/o i/o i/o i/o i/o vccio i/o i/o i/o i/o gnd vccint i/o i/o/pd1 i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o n/c n/c n/c n/c i/o vccio i/o i/o i/o/pd2 i/o n/c n/c n/c n/c i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o i/o vccio i/o i/o i/o i/o i/o n/c n/c n/c n/c i/o i/o i/o
3 atf1508as(l) 0784m ? 08/01 block diagram 8 to 12 16
4 atf1508as(l) 0784m ? 08/01 description the atf1508as is a high-performance, high-density complex programmable logic device (cpld) that utilizes atmel ? s proven electrically-erasable technology. with 128 logic macrocells and up to 100 inputs, it easily integrates logic from several ttl, ssi, msi, lsi and classic plds. the atf1508as ? s enhanced routing switch matrices increase usable gate count and increase odds of successful pin-locked design modifications. the atf1508as has up to 96 bi-directional i/o pins and four dedicated input pins, depending on the type of device package selected. each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. each of these control signals can be selected for use individually within each macrocell. each of the 128 macrocells generates a buried feedback that goes to the global bus. each input and i/o pin also feeds into the global bus. the switch matrix in each logic block then selects 40 individual signals from the global bus. each macrocell also generates a foldback logic term that goes to a regional bus. cascade logic between macrocells in the atf1508as allows fast, efficient generation of complex logic functions. the atf1508as contains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. the atf1508as macrocell, shown in figure 1, is flexible enough to support highly-complex logic functions operating at high speed. the macrocell consists of five sections: product terms and product term select multiplexer; or/xor/cascade logic, a flip-flop, output select and enable, and logic array inputs. unused macrocells are automatically disabled by the compiler to decrease power consump- tion. a security fuse, when programmed, protects the contents of the atf1508as. two bytes (16 bits) of user signature are accessible to the user for purposes such as storing project name, part number, revision or date. the user signature is accessible regardless of the state of the security fuse. the atf1508as device is an in-system programmable (isp) device. it uses the industry-stan- dard 4-pin jtag interface (ieee std. 1149.1), and is fully compliant with jtag ? s boundary- scan description language (bsdl). isp allows the device to be programmed without remov- ing it from the printed circuit board. in addition to simplifying the manufacturing flow, isp also allows design modifications to be made in the field via software. product terms and select mux each atf1508as macrocell has five product terms. each product term receives as its inputs all signals from both the global bus and regional bus. the product term select multiplexer (ptmux) allocates the five product terms as needed to the macrocell logic gates and control signals. the ptmux programming is determined by the design compiler, which selects the optimum macrocell configuration. or/xor/ cascade logic the atf1508as ? s logic structure is designed to efficiently support all types of logic. within a single macrocell, all the product terms can be routed to the or gate, creating a 5-input and/or sum term. with the addition of the casin from neighboring macrocells, this can be expanded to as many as 40 product terms with a little small additional delay. the macrocell ? s xor gate allows efficient implementation of compare and arithmetic func- tions. one input to the xor comes from the or sum term. the other xor input can be a product term or a fixed high- or low-level. for combinatorial outputs, the fixed level input allows polarity selection. for registered functions, the fixed levels allow demorgan minimiza- tion of product terms. the xor gate is also used to emulate t- and jk-type flip-flops.
5 atf1508as(l) 0784m ? 08/01 flip-flop the atf1508as ? s flip-flop has very flexible data and control functions. the data input can come from either the xor gate, from a separate product term or directly from the i/o pin. selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (this feature is automatically implemented by the fitter soft- ware). in addition to d, t, jk and sr operation, the flip-flop can also be configured as a flow- through latch. in this mode, data passes through when the clock is high and is latched when the clock is low. the clock itself can be either the global clk signal (gck) or an individual product term. the flip-flop changes state on the clock ? s rising edge. when the gck signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. when the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. the flip-flop ? s asynchronous reset signal (ar) can be either the global clear (gclear), a product term, or always off. ar can also be a logic or of gclear with a product term. the asynchro- nous preset (ap) can be a product term or always off. output select and enable the atf1508as macrocell output can be selected as registered or combinatorial. the buried feedback signal can be either combinatorial or registered signal regardless of whether the out- put is combinatorial or registered. the output enable multiplexer (moe) controls the output enable signals. any buffer can be permanently enabled for simple output operation. buffers can also be permanently disabled to allow use of the pin as an input. in this configuration all the macrocell resources are still avail- able, including the buried feedback, expander and cascade logic. the output enable for each macrocell can be selected as one of the global output enable signals. the device has six global oe signals. global bus/switch matrix the global bus contains all input and i/o pin signals as well as the buried feedback signal from all 128 macrocells. the switch matrix in each logic block receives as its inputs all signals from the global bus. under software control, up to 40 of these signals can be selected as inputs to the logic block. foldback bus each macrocell also generates a foldback product term. this signal goes to the regional bus and is available to 16 macrocells. the foldback is an inverse polarity of one of the macrocell ? s product terms. the 16 foldback terms in each region allows generation of high fan-in sum terms (up to 21 product terms) with a little additional delay. 3.3v or 5.0v i/o operation the atf1508as device has two sets of v cc pins viz, v ccint and v ccio . v ccint pins must always be connected to a 5.0v power supply. v ccint pins are for input buffers and are ? com- patible ? with both 3.3v and 5.0v inputs. v ccio pins are for i/o output drives and can be connected for 3.3/5.0v power supply. open-collector output option this option enables the device output to provide control signals such as an interrupt that can be asserted by any of the several devices.
6 atf1508as(l) 0784m ? 08/01 figure 1. atf1508as macrocell programmable pin-keeper option for inputs and i/os the atf1508as offers the option of programming all input and i/o pins so that ? pin-keeper ? circuits can be utilized. when any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. this circuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. the keeper circuits eliminate the need for external pull-up resistors and eliminate their dc power consumption. input diagram
7 atf1508as(l) 0784m ? 08/01 speed/power management the atf1508as has several built-in speed and power management features. the atf1508as contains circuitry that automatically puts the device into a low-power stand-by mode when no logic transitions are occurring. this not only reduces power consumption dur- ing inactive periods, but also provides proportional power-savings for most applications running at system speeds below 5 mhz. to further reduce power, each atf1508as macrocell has a reduced-power bit feature. this feature allows individual macrocells to be configured for maximum power savings. this feature may be selected as a design option. i/o diagram all atf1508 also have an optional power-down mode. in this mode, current drops to below 10 ma. when the power-down option is selected, either pd1 or pd2 pins (or both) can be used to power down the part. the power-down option is selected in the design source file. when enabled, the device goes into power-down when either pd1 or pd2 is high. in the power-down mode, all internal logic signals are latched and held, as are any enabled outputs. all pin transitions are ignored until the pd pin is brought low. when the power-down feature is enabled, the pd1 or pd2 pin cannot be used as a logic input or output. however, the pin ? s macrocell may still be used to generate buried foldback and cascade logic signals. all power-down ac characteristic parameters are computed from external input or i/o pins, with reduced-power bit turned on. for macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, trpa, must be added to the ac parameters, which include the data paths t lad , t lac , t ic , t acl , t ach and t sexp . each output also has individual slew rate control. this may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. outputs default to slow switching, and may be specified as fast switching in the design file.
8 atf1508as(l) 0784m ? 08/01 design software support atf1508as designs are supported by several third-party tools. automated fitters allow logic synthesis using a variety of high level description languages and formats. power-up reset the atf1508as is designed with a power-up reset, a feature critical for state machine initial- ization. at a point delayed slightly from v cc crossing v rst , all registers will be initialized, and the state of each output will depend on the polarity of its buffer. however, due to the asynchro- nous nature of reset and uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. the clock must remain stable during t d . the atf1508as has two options for the hysteresis about the reset level, v rst , small and large. during the fitting process users may configure the device with the power-up reset hys- teresis set to large or small. atmel pof2jed users may select the large option by including the flag ? -power_reset ? on the command line after ? filename.pof ? . to allow the registers to be properly reinitialized with the large hysteresis option selected, the following condition is added: 4. if v cc falls below 2.0v, it must shut off completely before the device is turned on again. when the large hysteresis option is active, i cc is reduced by several hundred microamps as well. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf1508as fuse patterns. once programmed, fuse verify is inhibited. however, user signature and device id remains accessible. programming atf1508as devices are in-system programmable (isp) devices utilizing the 4-pin jtag pro- tocol. this capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. atmel provides isp hardware and software to allow programming of the atf1508as via the pc. isp is performed by using either a download cable or a comparable board tester or a sim- ple microprocessor interface. to allow isp programming support by the automated test equipment (ate) vendors, serial vector format (svf) files can be created by the atmel isp software. conversion to other ate tester format beside svf is also possible atf1508as devices can also be programmed using standard third-party programmers. with third-party programmer, the jtag isp port can be disabled thereby allowing four additional i/o pins to be used for logic. contact your local atmel representatives or atmel pld applications for details.
9 atf1508as(l) 0784m ? 08/01 isp programming protection the atf1508as has a special feature that locks the device and prevents the inputs and i/o from driving if the programming process is interrupted for any reason. the inputs and i/o default to high-z state during such a condition. in addition the pin-keeper option preserves the former state during device programming. all atf1508as devices are initially shipped in the erased state thereby making them ready to use for isp. note: for more information refer to the ? designing for in-system programmability with atmel cplds ? application note. jtag-bst overview the jtag boundary-scan testing is controlled by the test access port (tap) controller in the atf1508as. the boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. each input pin and i/o pin has its own boundary-scan cell (bsc) in order to support boundary-scan testing. the atf1508as does not currently include a test reset (trst) input pin because the tap con- troller is automatically reset at power-up. the six jtag bst modes supported include: sample/preload, extest, bypass and idcode. bst on the atf1508as is imple- mented using the boundary-scan definition language (bsdl) described in the jtag specification (ieee standard 1149.1). any third-party tool that supports the bsdl format can be used to perform bst on the atf1508as. the atf1508as also has the option of using four jtag-standard i/o pins for in-system pro- gramming (isp). the atf1508as is programmable through the four jtag pins using programming compatible with the ieee jtag standard 1149.1. programming is performed by using 5v ttl-level programming signals from the jtag isp interface. the jtag feature is a programmable option. if jtag (bst or isp) is not needed, then the four jtag control pins are available as i/o pins. jtag boundary-scan cell (bsc) testing the atf1508as contains up to 96 i/o pins and four input pins, depending on the device type and package type selected. each input pin and i/o pin has its own boundary-scan cell (bsc) in order to support boundary-scan testing as described in detail by ieee standard 1149.1. a typical bsc consists of three capture registers or scan registers and up to two update regis- ters. there are two types of bscs, one for input or i/o pin, and one for the macrocells. the bscs in the device are chained together through the (bst) capture registers. input to the cap- ture register chain is fed in from the tdi pin while the output is directed to the tdo pin. capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. control signals are generated internally by the jtag tap controller. the bsc configuration for the input and i/o pins and macrocells are shown below.
10 atf1508as(l) 0784m ? 08/01 bsc configuration pins and macrocells (except jtag tap pins ) note: the atf1508as has pull-up option on tms and tdi pins. this feature is selected as a design option. bsc configuration for macrocell boundary scan definition language (bsdl) models for the atf1508 these are now available in all package types via the atmel web site. these models can be used for boundary-scan test operation in the atf1508as and have been scheduled to con- form to the ieee 1149.1 standard. 0 1 0 1 dq dq capture dr update dr 0 1 0 1 dq dq tdi outj oej shift clock mode tdo macrocell bsc pin
11 atf1508as(l) 0784m ? 08/01 pci compliance the atf1508as also supports the growing need in the industry to support the new peripheral component interconnect (pci) interface standard in pci-based designs and specifications. the pci interface calls for high current drivers, which are much larger than the traditional ttl drivers. pci voltage-to- current curves for +5v signaling in pull-up mode pci voltage-to- current curves for +5v signaling in pull-down mode 2.4 vcc 1.4 -2 -44 -178 current (ma) ac drive point dc drive point voltage pull up test point 2.2 vcc 0.55 3.6 95 380 current (ma) ac drive point dc drive point voltage pull down test point
12 atf1508as(l) 0784m ? 08/01 note: 1. leakage current is without pin-keeper off. notes: 1. equation a: i oh = 11.9 (v out - 5.25) * (v out + 2.45) for v cc > v out > 3.1v. 2. equation b: i ol = 78.5 * v out * (4.4 - v out ) for 0v < v out < 0.71v. pci dc characteristics symbol parameter conditions min max units v cc supply voltage 4.75 5.25 v v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage -0.5 0.8 v i ih input high leakage current (1) v in = 2.7v 70 a i il input low leakage current (1) v in = 0.5v -70 a v oh output high voltage i out = -2 ma 2.4 v v ol output low voltage i out = 3 ma, 6 ma 0.55 v c in input pin capacitance 10 pf c clk clk pin capacitance 12 pf c idsel idsel pin capacitance 8pf l pin pin inductance 20 nh pci ac characteristics symbol parameter conditions min max units i oh(ac) switching 0 < v out 1.4 -44 ma current high 1.4 < v out < 2.4 -44+(v out - 1.4)/0.024 ma 3.1 < v out < v cc equation a (1) ma (test high) v out = 3.1v -142 a i ol(ac) switching v out >2.2v 95 ma current low 2.2 > v out > 0 v out /0.023 ma 0.1 > v out > 0 equation b (2) ma (test point) v out = 0.71 206 ma i cl low clamp current -5 < v in -1 -25+(v in + 1)/0.015 ma slew r output rise slew rate 0.4v to 2.4v load 0.5 3.0 v/ns slew f output fall slew rate 2.4v to 0.4v load 0.5 3.0 v/ns
13 atf1508as(l) 0784m ? 08/01 power-down mode the atf1508as includes two pins for optional pin-controlled power-down feature. when this mode is enabled, the pd pin acts as the power-down pin. when the pd1 and pd2 pin is high, the device supply current is reduced to less than 10 ma. during power-down, all output data and internal logic states are latched and held. therefore, all registered and combinatorial out- put data remain valid. any outputs that were in a high-z state at the onset will remain at high- z. during power-down, all input signals except the power-down pin are blocked. input and i/o hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. the power-down pin feature is enabled in the logic design file. designs using either power-down pin may not use the pd pin logic array input. however, bur- ied logic resources in this macrocell may still be used. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. power-down ac characteristics (1)(2) symbol parameter -7 -10 -15 -20 -25 units minmaxminmaxminmaxminmaxminmax t ivdh valid i, i/o before pd high 7 10 15 20 25 ns t gvdh valid oe (2) before pd high 7 10 15 20 25 ns t cvdh valid clock (2) before pd high 7 10 15 20 25 ns t dhix i, i/o don ? t care after pd high 12 15 25 30 35 ns t dhgx oe (2) don ? t care after pd high 12 15 25 30 35 ns t dhcx clock (2) don ? t care after pd high 12 15 25 30 35 ns t dliv pd low to valid i, i/o 1 1 1 1 1 s t dlgv pd low to valid oe (pin or term) 1 1 1 1 1 s t dlcv pd low to valid clock (pin or term) 1 1 1 1 1 s t dlov pd low to valid output 1 1 1 1 1 s absolute maximum ratings* temperature under bias.................................. -40 c to +85 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1)
14 atf1508as(l) 0784m ? 08/01 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. dc and ac operating conditions commercial industrial operating temperature (ambient) 0 c - 70 c-40 c - 85 c v ccint or v ccio (5v) power supply 5v 5% 5v 10% v ccio (3.3v) power supply 2.7v - 3.6v 2.7v - 3.6v dc characteristics (1) symbol parameter condition min typ max units i il input or i/o low leakage current v in = v cc -2 -10 a i ih input or i/o high leakage current 210a i oz tri-state output off-state current v o = v cc or gnd -40 40 a i cc1 power supply current, standby v cc = max v in = 0, v cc std mode com. 160 ma ind. 180 ma ? l ? mode com. 10 a ind. 10 a i cc2 power supply current, power-down mode v cc = max v in = 0, v cc ? pd ? mode 1 10 ma i cc3 (2) reduced-power mode supply current v cc = max v in = 0, v cc std mode com. 65 ma ind. 85 ma v ccio supply voltage 5.0v device output com. 4.75 5.25 v ind. 4.5 5.5 v v ccio supply voltage 3.3v device output 3.0 3.6 v v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v ccio + 0.3 v v ol output low voltage (ttl) v in = v ih or v il v ccio = min, i ol = 12 ma com. 0.45 v ind. 0.45 v output low voltage (cmos) v in = v ih or v il v cc = min, i ol = 0.1 ma com. 0.2 v ind. 0.2 v v oh output high voltage (ttl) v in = v ih or v il v ccio = min, i oh = -4.0 ma 2.4 v
15 atf1508as(l) 0784m ? 08/01 note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. the ogi pin (high-volt - age pin during programming) has a maximum capacitance of 12 pf. timing model input test waveforms and measurement levels r r , t f = 1.5 ns typical output ac test loads note: *numbers in parenthesis refer to 3.0v operating conditions (preliminary). pin capacitance (1) typ max units conditions c in 810 pf v in = 0v; f = 1.0 mhz c i/o 810 pf v out = 0v; f = 1.0 mhz u (3.0v)* (703 )* (8060 )*
16 atf1508as(l) 0784m ? 08/01 ac characteristics (1) symbol parameter -7 -10 -15 -20 -25 units min max min max min max min max min max t pd1 input or feedback to non-registered output 7.5 10 3 15 20 25 ns t pd2 i/o input or feedback to non-registered feedback 793121620ns t su global clock setup time 6 7 11 16 20 ns t h global clock hold time 0 0 0 0 0 ns t fsu global clock setup time of fast input 3 3333ns t fh global clock hold time of fast input 0.5 0.5 1.0 1.5 2 mhz t cop global clock to output delay 4.5 5 8 10 13 ns t ch global clock high time 3 4 5 6 7 ns t cl global clock low time 3 4 5 6 7 ns t asu array clock setup time 3 3 4 4 5 ns t ah array clock hold time 2 3 4 5 6 ns t acop array clock output delay 7.5 10 15 20 25 ns t ach array clock high time 3 4 6 8 10 ns t acl array clock low time 3 4 6 8 10 ns t cnt minimum clock global period 8 10 13 17 22 ns f cnt maximum internal global clock frequency 125 100 76.9 66 50 mhz t acnt minimum array clock period 8 10 13 17 22 ns f acnt maximum internal array clock frequency 125 100 76.9 66 50 mhz f max maximum clock frequency 166.7 125 100 41.7 33.3 mhz t in input pad and buffer delay 0.5 0.5 2 2 2 ns t io i/o input pad and buffer delay 0.5 0.5 2 2 2 ns t fin fast input delay 1 1 2 2 2 ns t sexp foldback term delay 4 5 8 10 12 ns t pexp cascade logic delay 0.8 0.8 1 1 1.2 ns t lad logic array delay 3 5 6 7 8 ns t lac logic control delay 3 5 6 7 8 ns t ioe internal output enable delay 2 2 3 3 4 ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l = 35 pf) 21.5 4 5 6ns
17 atf1508as(l) 0784m ? 08/01 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac ,t tic , t acl , and t sexp parameters for macrocells running in the reduced- power mode. t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l = 35 pf) 2.5 2.0 5 6 7 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio = 5v or 3.3v; c l = 35 pf) 55.5 8 1012ns t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5.0v; c l = 35 pf) 4.0 5.0 7 9 10 ns t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l = 35 pf) 4.5 5.5 7 9 10 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5.0v/3.3v; c l = 35 pf) 9 9 10 11 12 ns t xz output buffer disable delay (c l = 5 pf) 45678ns t su register setup time 3 2 4 5 6 ns t h register hold time 2 3 4 5 6 ns t fsu register setup time of fast input 3 3223ns t fh register hold time of fast input 0.5 0.5 2 2 2.5 ns t rd register delay 1 2 1 2 2 ns t comb combinatorial delay 1 2 1 2 2 ns t ic array clock delay 3 5 6 7 8 ns t en register enable time 3 5 6 7 8 ns t glob global control delay 1 1 1 1 1 ns t pre register preset time 2 3 4 5 6 ns t clr register clear time 2 3 4 5 6 ns t uim switch matrix delay 1 1 2 2 2 ns t rpa reduced-power adder (2) 10 11 13 14 15 ns ac characteristics (continued) (1) symbol parameter -7 -10 -15 -20 -25 units min max min max min max min max min max
18 atf1508as(l) 0784m ? 08/01 supply current vs. supply voltage (t a = 25 c, f = 0) 50.0 100.0 150.0 200.0 250.0 4.50 4.75 5.00 5.25 5.50 v cc (v) i cc (ma) standard power reduced power mode supply current vs. supply voltage low-power ("l") version (t a = 25 c, f = 0) 0.0 10.0 20.0 30.0 4.50 4.75 5.00 5.25 5.50 v cc (v) i cc ( a) supply current vs. frequency standard power (t a = 25 c, f = 0) 0.0 50.0 100.0 150.0 200.0 250.0 300.0 0.00 20.00 40.00 60.00 80.00 100.00 frequency (mhz) i cc ( a) standard power reduced power mode supply current vs. supply voltage pin-controlled power-down mode (t a = 25 c, f = 0) 700.0 800.0 900.0 1000.0 1100.0 4.50 4.75 5.00 5.25 5.50 v cc (v) i cc ( a) standard power reduced power mode supply current vs. frequency low-power ("l") version (t a = 25 c) 0.0 50.0 100.0 150.0 200.0 0.00 5.00 10.00 15.00 20.00 frequency (mhz) i cc (ma) standard power reduced power mode
19 atf1508as(l) 0784m ? 08/01 output source current vs. supply voltage (voh = 2.4v, t a = 25 c) -60 -50 -40 -30 -20 -10 0 4.50 4.75 5.00 5.25 5.50 supply voltage (v) ioh (ma) input clamp current vs. input voltage (v cc = 5v, t a = 25 c) -160 -140 -120 -100 -80 -60 -40 -20 0 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 input voltage (v) input current (ma) output sink current vs. supply voltage (vol = 0.5v, t a = 25 c) 36 37 38 39 40 41 42 43 4.50 4.75 5.00 5.25 5.50 supply voltage (v) iol (ma) output source current vs. supply voltage (v cc = 5v, t a = 25 c) -110 -90 -70 -50 -30 -10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output voltage (v) ioh (ma) input current vs. input voltage (v cc = 5v, t a = 25 c) -30 -20 -10 0 10 20 30 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 input voltage (v) input current ( a) output sink current vs. output voltage (v cc = 5v, t a = 25 c) 0 20 40 60 80 100 120 140 0.00.51.01.52.02.53.03.54.04.55.0 output voltage (v) iol (ma)
20 atf1508as(l) 0784m ? 08/01 normalized tpd vs. supply voltage (t a = 25 c) 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50 supply voltage (v) normalized tpd normalized tco vs. supply voltage (t a = 25 c) 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50 supply voltage (v) normalized tpd normalized tsu vs. supply voltage (t a = 25 c) 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50 supply voltage (v) normalized tsu normalized tpd vs. temperature (v cc = 5.0v) 0.80 0.90 1.00 1.10 1.20 -40 0 25 75 temperature (c) normalized tpd normalized tco vs. temperature (v cc = 5.0v) 0.80 0.90 1.00 1.10 1.20 -40 0 25 75 temperature (c) normalized tco normalized tsu vs. temperature (v cc = 5.0v) 0.80 0.90 1.00 1.10 1.20 -40 0 25 75 temperature (c) normalized tsu
21 atf1508as(l) 0784m ? 08/01 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power-down pins tdi, tms, tck, tdo jtag pins used for boundary scan testing or in-system programming gnd ground pins vccint vcc pins for the device (+5v - internal) vccio vcc pins for output drivers (for i/o pins) (+5v or 3.3v - i/os) atf1508as dedicated pinouts dedicated pin 84-lead j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp input/oe2/gclk2 2 92 90 142 input/gclr 1 91 89 141 input/oe1 84 90 88 140 input/gclk1 83 89 87 139 i/o /gclk3 81 87 85 137 i/o / pd (1, 2) 12,45 3,43 1,41 63,159 i/o / tdi(jtag) 14 6 4 9 i/o / tms(jtag) 23 17 15 22 i/o / tck(jtag) 62 64 62 99 i/o / tdo(jtag) 71 75 73 112 gnd 7,19,32,42, 47,59,72,82 13,28,40,45, 61,76,88,97 11,26,38,43, 59,74,86,95 17,42,60,66,95, 113,138,148 vccint 3,43 41,93 39,91 61,143 vccio 13,26,38, 53,66,78 5,20,36,53,68,84 3,18,34,51,66,82 8,26,55,79,104,133 n/c ?? ? 1,2,3,4,5,6,7,34,35,36, 37,38,39,40,44,45,46, 47,74,75,76,77,81,82, 83,84,85,86,87,114, 115,116,117,118,119, 120,124,125,126,127, 154,155,156,157 # of signal pins 68 84 84 100 # user i/o pins 64 80 80 96
22 atf1508as(l) 0784m ? 08/01 atf1508as i/o pinouts mc plb 84-lead j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp mc plb 84-lead j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp 1a ? 4 2 160 33 c ? 27 25 41 2a ???? 34 c ???? 3 a/ pd1 12 3 1 159 35 c 31 26 24 33 4a ?? ? 158 36 c ?? ? 32 5 a 11 2 100 153 37 c 30 25 23 31 6 a 10 1 99 152 38 c 29 24 22 30 7a ???? 39 c ???? 8 a 9 100 98 151 40 c 28 23 21 29 9a ? 99 97 150 41 c ? 22 20 28 10 a ???? 42 c ???? 11 a 8 98 96 149 43 c 27 21 19 27 12 a ?? ? 147 44 c ?? ? 25 13 a 6 96 94 146 45 c 25 19 17 24 14 a 5 95 93 145 46 c 24 18 16 23 15 a ???? 47 c ???? 16 a 4 94 92 144 48 c/ tms 23 17 15 22 17 b 22 16 14 21 49 d 41 39 37 59 18 b ???? 50 d ???? 19 b 21 15 13 20 51 d 40 38 36 58 20 b ?? ? 19 52 d ?? ? 57 21 b 20 14 12 18 53 d 39 37 35 56 22 b ? 12 10 16 54 d ? 35 33 54 23 b ???? 55 d ???? 24 b 18 11 9 15 56 d 37 34 32 53 25 b 17 10 8 14 57 d 36 33 31 52 26 b ???? 58 d ???? 27 b 16 9 7 13 59 d 35 32 30 51 28 b ?? ? 12 60 d ?? ? 50 29 b 15 8 6 11 61 d 34 31 29 49 30 b ? 751062d ? 30 28 48 31 b ???? 63 d ???? 32 b/ tdi 14 6 4 964d33292743 65 e 44 42 40 62 97 g 63 65 63 100
23 atf1508as(l) 0784m ? 08/01 66 e ???? 98 g ???? 67 e/ pd2 45 43 41 63 99 g 64 66 64 101 68 e ?? ? 64 100 g ?? ? 102 69e46444265101g656765103 70 e ? 46 44 67 102 g ? 69 67 105 71 e ???? 103 g ???? 72e48474568104g677068106 73e49484669105g687169107 74 e ???? 106 g ???? 75e50494770107g697270108 76 e ?? ? 71 108 g ?? ? 109 77e51504872109g707371110 78 e ? 51 49 73 110 g ? 74 72 111 79 e ???? 111 g ???? 80e52525078112 g/ tdo 71 75 73 112 81 f ? 54 52 80 113 h ? 77 75 121 82 f ???? 114 h ???? 83f54555388115h737876122 84 f ?? ? 89 116 h ?? ? 123 85f55565490117h747977128 86f56575591118h758078129 87 f ???? 119 h ???? 88f57585692120h768179130 89 f ? 59 57 93 121 h ? 82 80 131 90 f ???? 122 h ???? 91f58605894123h778381132 92 f ?? ? 96 124 h ?? ? 134 93f60626097125h798583135 94f61636198126h808684136 95 f ???? 127 h ???? 96 f/ tck 62 64 62 99 128 h/ gclk3 81 87 85 137 atf1508as i/o pinouts (continued) mc plb 84-lead j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp mc plb 84-lead j-lead 100-lead pqfp 100-lead tqfp 160-lead pqfp
24 atf1508as(l) 0784m ? 08/01 using ? c ? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ? i ? to the ? c ? device (7 ns ? c ? = 10 ns ? i ? ) and de-rate power by 30%. atf1508as ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 7.5 4.5 166.7 atf1508as-7 jc84 atf1508as-7 qc100 atf1508as-7 ac100 atf1508as-7 qc160 84j 100q 100a 160q commercial (0 c to 70 c) 10 5 125 atf1508as-10 jc84 atf1508as-10 qc100 atf1508as-10 ac100 atf1508as-10 qc160 84j 100q 100a 160q commercial (0 c to 70 c) 10 5 125 atf1508as-10 jl84 atf1508as-10 ql100 atf1508as-10 al100 atf1508as-10 ql160 84j 100q 100a 160q industrial (-40 c to +85 c) 15 5 100 atf1508as-15 jc84 atf1508as-15 qc100 atf1508as-15 ac100 atf1508as-15 qc160 84j 100q 100a 160q commercial (0 c to 70 c) 15 8 100 atf1508as-15 ji84 atf1508as-15 qi100 atf1508as-15 ai100 atf1508as-15 qi160 84j 100q 100a 160q industrial (-40 c to +85 c) package type 84j 84-lead, plastic j-leaded chip carrier (plcc) 100q 100-lead, plastic quad pin flat package (pqfp) 100a 100-lead, very thin plastic gull wing quad flat package (tqfp) 160q 160-lead, plastic quad pin flat package (pqfp)
25 atf1508as(l) 0784m ? 08/01 using ? c ? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ? i ? to the ? c ? device (7 ns ? c ? = 10 ns ? i ? ) and de-rate power by 30%. atf1508asl ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 20 12 83.3 atf1508asl-20 jc84 atf1508asl-20 qc100 atf1508asl-20 ac100 atf1508asl-20 qc160 84j 100q 100a 160q commercial (0 c to 70 c) 25 15 70 atf1508asl-25 jc84 atf1508asl-25 qc100 atf1508asl-25 ac100 atf1508asl-25 qc160 84j 100q 100a 160q commercial (0 c to 70 c) 25 15 70 atf1508asl-25 ji84 atf1508asl-25 qi100 atf1508asl-25 ai100 atf1508asl-25 qi160 84j 100q 100a 160q industrial (-40 c to +85 c) package type 84j 84-lead, plastic j-leaded chip carrier (plcc) 100q 100-lead, plastic quad pin flat package (pqfp) 100a 100-lead, very thin plastic gull wing quad flat package (tqfp) 160q 160-lead, plastic quad pin flat package (pqfp)
26 packaging information atf1508as(l) 0784m ? 08/01 1.158(29.4) 1.150(29.2) 1.195(30.4) 1.185(30.1) 0.0125(0.318) 0.0075(0.191) 0.021(0.053) 0.013(0.330) 1.00 ref sq sq .032(.813) .026(.660) sq .050(1.27) typ .045 x 45? pin no. 1 identify .045(1.14) x 30? - 45? 1.13(38.7) 1.09(27.7) .120(3.05) .090(2.29) .020(0.51) min .180(4.57) .165(4.19) .020(0.51) x 45? max (3x) *controlling dimension: millimeters pin 1 id 16.95 (0.667) 17.44 (0.687) 19.87 (.782) 20.12 (.792) 22.95 (0.904) 23.45 (0.923) 0.65 (0.026) bsc 0.22 (0.009) 0.41 (0.016) 3.40 (.134) max 0.10 (0.004) min 0.73 (0.028) 1.03 (0.041) 13.87 (0.546) 14.12 (0.556) 0.10 (0.004) 0.25 (0.010) 0 7 *controlling dimension: millimeters pin 1 id 0.56(0.022) 0.44(0.018) 16.25(0.640) 15.75(0.620) 0.27(0.011) 0.17(0.007) 14.10(0.555) 13.90(0.547) 0.15(0.006) 0.05(0.002) 0.75(0.030) 0.45(0.018) 0-7 0.20(0.008) 0.10(0.004) 1.05(0.041) 0.95(0.037) *controlling dimension: millimeters 1.218(30.95) 1.238(31.45) sq .008(0.20) .016(0.40) pin 1 id .0256(0.65) bsc 1.098(27.90) 1.106(28.10) sq .127(3.22) .157(3.97) .002(0.05) .020(0.50) .025(0.65) .037(0.95) 0 7 .004(0.10) .009(0.23) 84j , 84-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 af 100q , 100-lead, plastic gull wing quad flat package (pqfp) dimensions in millimeters and (inches) 100a , 100-lead, very thin (1.0 mm) plastic gull wing quad flat package (tqfp) dimensions in millimeters and (inches)* 160q , 160-lead, plastic gull wing quad flat package (pqfp) dimensions in millimeters and (inches)
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